Static inverter



2 Sheets-Sheet 1 E. M. SCHMIDT STATIC INVERTER May 28, 1963 Filed March6, 1959 May 28, 1963 E. M. SCHMIDT STATIC INVERTER 2 Sheets-Sheet 2Filed March 6, 1959 Y i m M J r m i mw* n g A I v v h '4 h .Q 4 ##T OSQWP HT 1 6? p N? Q United States 3,fi91,729 Patented May 28, 19633,091,729 STATIC INVERTER Edward M. Schmidt, Chicago, 111., assignor toBorg-Warner Corporation, Chicago, IEL, a corporation of Illinois FiledMar. 6, 1959, Ser. No. 797,803 6 Claims. (Cl. 321) This inventionrelates to a static inverter for producing a polyphase alternatingcurrent voltage from a direct current source.

This invention constitutes an improvement to my previously filedapplication, Serial No. 745,412, filed June 30, 1958, now Paten-t No.2,953,735.

Inverters of the vibratory and rotary types are well known in the art.These inverters are known to work satisfactorily for certainapplications; however, they have several inherent limitations. Some ofthese limitations are: low efficiency and excessive weight per watt ofpower output; they are affected by changes in temperature andenvironment; the frequency and phase are unstable and are affected bychanges in load; and because of their moving parts, they requireconsiderable maintenance.

It is an object of the present invention to provide a static inverter ofcomparatively light weight that is maintenance free and is unaffected byordinary environmental changes.

It is another object to provide a static inverter employing a timinggenerator and a logic control circuit for converting a direct currentvoltage to a polyphase alternating current voltage.

It is still another object to provide a static inverter employing aplurality of controlled rectifier transistors, a plurality of magneticshift registers for controlling the conduction of the rectifiers, and atiming pulse generator for controlling the operation of the shiftregisters.

It is still another object to provide an improved static FIG. 1 is ablock diagram of the static inverter of the present invention, includinga timing pulse generator, a logic control circuit, a plurality ofcontrolled rectifiers, a power transformer, and a voltage regulator;

FIG. 2 is a schematic diagram of portions of the static invertersuperimposed on the block diagram of FIG. 1;

FIG. 3 is a schematic diagram of the timing pulse generator; and

FIG. 4 is a schematic diagram of the voltage regulator and powertransformer.

Like characters of reference designate like parts i-n the several views.

The static inverter of the present invention, shown in FIG. 1, isdesignated generally by the numeral 10, and comprises a timing pulsegenerator 11, a logic control circuit 12, a plurality of controlledrectifier type transistors 13-18, a power transformer 19, and a voltageregulator 20. The output of the pulse generator 11 is connected to theinput of the logic control circuit 12.

Each of the controlled rectifier circuits 13-18 has an input connectionand an output connection with the inputs respectively connected to thelogic circuit and the outputs respectively connected to the powertransformer 19. The voltage regulator 24} is connected to the outputside of the power transformer 19 and functions to control the outm asput voltage under varying load conditions as will be describedhereinafter.

Referring now to FIG. 2, the logic control circuit is seen to comprise aplurality of magnetic shift registers 21-26. Each of the shift registershas a magnetic core 27 and four windings 28, 29, 30, and 31 which areadapted to affect the magnetic saturation of the core 27. The winding 28of the shift register 23 constitutes a shift winding and is connected inseries with corresponding shift windings for each of the other fiveshift registers. The timing pulse generator 11 is connected by means ofconductors 32 and 33 to the series circuit comprising the shift windingsof the several shift registers 21-26. The winding 29 is an input windingand is connected to the output winding 30 of the preceding shiftregister. The output winding 30 is connected through a temporary storagecircuit 34 to the input winding 29 of the following shift register.

The storage circuit 34 comprises a capacitor 35, an inductor 36, aresistor 37, and a diode 38. One end of the coil 30 is connected throughthe series circuit of the diode 38, the inductor 36 and resistor 37 toone end of a winding 29 in the shift register 24. A capacitor 35connects the other end of the winding 30 to a junction 39 between thediode 38 and coil 36. The junction 39 constitutes an output connectionwhich leads to an input of the controlled rectifier circuit 15. Thewinding 31 constitutes a reset winding which is connected between 'adirect current power line 40 and a ground line 41. Correspondingwindings 31 for each of the other shift registers are also connected inparallel between the lines 49 and 41. The polarity of the windings 31for five of the shift registers is in the same direction and thepolarity of the sixth reset winding 31 is reversed.

The circuit for each of the controlled rectifiers 13-18 comprises acontrolled rectifier type transistor 42, a buffer transistor 43, and adiode 44. The transistor 43 has a base 4312, an emitter 43c, and acollector 430. The base 43b is connected to the junction 39 of the shiftregister 23. The emitter 43c is connected to the anode of the diode 44,and the collector 430 is connected through a resistor 45 to a positiveD.C. source. The controlled rectifier transistor 42 has an anode 42a, acathode 42c and a gate 42g. The gate 42g is connected to the cathode :ofthe diode 44. The cathode 420 is connected to a ground line 46, and theanode 42a is connected to one end of a primary winding 47 of the powertransformer 19.

The circuit for the controlled rectifier 16 comprises a controlledrectifier type transistor 48, a buffer transistor 49, and a diode 50.The buffer transistor 49 has a base 4% connected to the output of theshift register 26, a

collector 490 connected through the resistor 45 to the D.C. source, andan emitter 492: connected to the anode of the diode 50. The controlledrectifier t-ransistor 48 comprises an anode 48a, a cathode 48c, and agate 48g. The gate 48g is connected to the cathode of the diode St thecathode 48c is connected to the ground line 46, and the anode 48a isconnected to the other end of the power transformer winding 47. Acommutating capacitor 51 is connected between the anodes 42a and 4811. Ashaping coil 52 is connected between a center tap of the winding 47 anda positive D.C. line 53. Accordingly lines 46 and 53 comprise means forapplying a D.C. voltage to the controlled rectifiers :15 and 16 toenergize these current conducting means.

To complete the circuit for the static inverter It the output of theshift register 21 is connected to the input of the rectifier 13; theoutput of the shift register 22 is connected to the input of therectifier 13; the output of the shift register 24 is connected to theinput of the rectiher 14; the output of the shift register 25 isconnected to the input of the rectifier 17; and the output of therectifier 26 is connected to the input of the rectifier 16. Thecontrolled 'rectifiers 13 and 14 and 17 and 18 are operable in pairs, asare the controlled rectifiers 15 and 16. The outputs of the rectifiers13 and 14 and of the rectifiers 17 and .18 are respectively connected toprimary windings of the power transformer 13. The reset line 40 isconnected through a resistor 54 and a reset switch 65 to a positive DC.source.

In operation, the gate circuit means or shift registers 21 and 26 areinitially conditioned for operation by momentarily closing the resetswitch 55. Closing the reset switch 55 allows the current to flowthrough each of the reset windings 31, saturating the respective cores27. Each of the core 27 is saturated in the same direction except forthe one for which the polarity of the reset Winding 31 is reversed.

The timing pulse generator 11 provides an output in the form of a seriesof narrow pulses of one polarity which are fed through the conductors 32and 33 and through the series of shift windings 28 of the shiftregisters 21-26. Depending upon the direction of saturation of fluxwithin each of the cores 27, each pulse will either switch the core 27or leave it in its previously saturated condition. Only one of the cores27 will be shifted by each of the pulses. Shifting the direction ofsaturation of the core 27 induces a voltage in a winding 38 which isapplied through a diode 38 to a controlled rectifier circuit, andthrough a temporary storage circuit 3- to the input winding 29 of thesucceeding shift register. The storage circuit 34 functions to delay thetransfer of energy to the input coil 29' of the succeeding shiftregister until the particular triggering pulse from the generater 11 hasterminated. The voltage applied from the output winding 38 to thesucceeding input winding 29' conditions the respective core 27 forshifting by the next pulse from pulse generator 11. As each of the shiftregisters is shifted, the output pulse supplied therefrom is effectiveto change the state of conduction of a connected controlled rectifiercircuit.

The output pulse from the junction 39 to the base 43b of the transistor43 is transmitted through the transistor 4-3 and the diode 44 to thegate 42g of the controlled rectifier transistor 42. This incoming pulseis effective to switch the transistor 42 from a state of non-conductionto a state of conduction. As the transistor 42 is triggered intoconduction, the voltage at the anode 42:: drops abruptly, which voltageis applied through the capacitor 51 to the anode 48a, switching thetransistor 48 from a conducting condition to a non-conducting condition.The substantial change in voltage at the anode 42a causes current toflow from the DC. line 53 through the shaping coil 52 and the primarywinding 47. Current flowing through the primary Winding 47 induces avoltage in the secondary of the power transformer 19 as will bedescribed hereinafter.

It should be noted, considering the shifting of all six registers 21 to26, to constitute a complete cycle of operation, that each shiftregister 21-26 is effective to control the conduction of one of therectifiers 13- 18 for 60 of the cycle. In this regard, it should benoted that the shift register 23 is connected to the input of therectifier 15 and the shift register 26 is connected to the rectifier 16so that their conduction is 180 out of phase with each other. Similarly,the rectifiers 13 and 14 are connected to the registers 21 and 24-respectively, and the rectifiers 17 and 18 are connected to theregisters 25 and 22 respectively. Moreover, the conduction of the rectifiers 13 and '14 is 120 out of phase with the conduction of therectifiers I and 16 and, correspondingly, also 120 out of phase with theconduction of the rectifiers 17 and '18.

Referring now to FIG. 3, there is illustrated a schematic diagram of acircuit that may be utilized for the timing pulse generator 11. Thecircuit comprises a unijunction transistor 60', a driver transistor 61,capacitors 62, 63, 64, and 65, resistors 66, 67, 63, 69, and 70, and avariable resistor 71. One end of the resistor 66 is connected to apositive D.C. source and the other end is connected to the conductor 33.The capacitor 62 is connected between the conductor 33 and a ground line72. The resistor 66 and capacitor 62 comprise an input filter for theDC. voltage supplied to the pulse generator 11. The resistor 67,variable resistor 71, and capacitor 63 are connected in series betweenthe conductor 33 and the ground 'line 72. The uni-junction transistor 60has an emitter 60: and two bases 60b and 6011 The emitter 60:2 isconnected to a junction between the variable resistor 71 and thecapacitor 63. The base 68% is connected to the conductor 33, and thebase 6lb is connected through the resistor 68 to the ground line 72. Thebase 6011 is also connected through a capacitor 64 and resistor 69 tothe ground line 72. The transistor 61 has a base 61b, a collector 61c,and an emitter 61a. The base 61b is connected to a junction between thecapacitor 64 and resistor 69; the collector 610 is connected through theresistor 70 to the conductor 32; and the emitter 61a is connecteddirectly to the ground line 72. The capacitor 65 is connected betweenthe conductor 32 and ground line 72.

In operation, the circuit functions as follows: A positive DC. voltageis supplied from the source through the resistor 66 to the conductor 33.The positive voltage appearing on the conductor 33 is applied to thebase 6812 The transistor 60 has a negative resistance characteristic,and within a certain operating range it has a state of low or negligibleconduction and a state of high conduction. Current flowing from the line33 through the resistors 67 and 71 charges the capacitor 63 and producesan increase in the voltage appearing at the emitter 69c. When thevoltage at the emitter 60@ reaches a predetermined magnitude, thetransistor 69 switches from its state of low conduction to its state ofhigh conduction. In the state of high conduction, current flowingthrough the base 60% develops a comparatively large positive voltageacross the resistor 68. This voltage is applied through the capacitor64, transistor 61, and resistor 70 to the conductor 32. The transistor61 functions to amplify the voltage developed across the resistor 68.When the transistor 60 is switched into a state of high con duction, thecapacitor 63 is discharged through the emitter 602 and base 6812 andwhen the voltage drops to a predetermined magnitude, the transistorshifts back from its state of high conduction to its state of lowconduction. The cycle is then repeated and the output developed is inthe form of a series of narrow pulses which are applied through theconductors 32 and 33 to the shift windings 28 of the shift registers21-26. The frequency generated by the pulse generator 11 is determinedby the time constant of the combined values of resistor 67 and theeffective portion of variable resistor 71 and the capacitor 63.

Referring now to FIG. 4, there is illustrated a schematic diagram of thevoltage regulator 20 as utilized with the power transformer 19. Thepower transformer 19 comprises three primary windings, 47, 86, and 81,and secondary windings 82, 83, and 84. One end of each of the secondarywindings 82-84 is connected to a common terminal designated by N. Theother ends of each of the secondary windings 82-84 comprise the outputterminals designatedas A, B, and C, respectively.

Three input or ternary windings for the voltage regulator 20 areprovided in the secondary of the transformer 19 and are designated bynumerals 85, 86, and 87. One end of each of the windings 85-87 isconnected to a common tie-line 88. The other ends of each of thewindings 85-87 constitute the input connections to the volt ageregulator 20 and are designated as a, b, and 0, respectively. Thevoltage regulatorcircuit also comprises three saturable reactors 89, 90,and 91, and three capacitors 92, 93, and 94. The capacitors 92, 93, and94 are connected across the secondary windings 82, 83, and 84,respectively. The saturable reactors 89-91 each have control windings95, 96, and 97, respectively, and secondary windings 98, 99, and 100.Each of the secondary windings 98-100 comprises two coils connected inseries which are wound in opposition to each other so that there is zeroinduced voltage in the control windings. Also, each of the secondarywindings 98-100 is connected in parallel with the secondary windings82-84, respectively.

It is also contemplated that the saturable reactors 89- 91 andcapacitors 92-94 may either be connected across the primary windings 47,80, and 81 or across the secondary windings 82-84. Moreover, thesecondary windings 82-84 may also be used as input windings to thevoltage regulator 20 in place of the ternary windings 85-87.

The voltage regulator 20 also comprises three transistors 101, 102, and103, diodes 104, 105, 106, 107, 108, 109, and 110 and three Zener diodes111, 112, and 113, and resistors 114 and 115. The diodes 104-109collectively comprise a bridge rectifier designated generally by theletter G. The diodes 104 and 105 are connected in series between atie-line 116 and a ground line 117. The pairs of diodes 106 and 107, and108 and 109 are similarly connected. The junction between each pair ofdiodes is connected to the points a, b, and c respectively.

The transistor 101 has a base 101b, a collector 101a, and an emitter10162. The base 101b is connected through the series circuit of Zenerdiodes 112, 111, and resistor 114 to the tie-line 116. The base 1010 isalso connected through the resistor 115 to the ground line 117. Theemitter 1011s is connected through the diode 113 to the ground line 117.The transistor 102 has a base 102b, a collector 1020, and an emitter102e. The base 102b is connected to the collector 1010, and the emitter102e is connected to a positive D.C. line 118. The transistor 103 has abase 10317, a collector 1030, and an emitter 103a. The base 103b isconnected to the collector 1020, the emitter 103e is connected to theground line 117, and the collector 1030 is connected through a conductor119 to one end of the winding 97. The windings 95, 96, and 97 areconnected in series between the DC. line 118 and the conductor 119. Thediode 110 is also connected between the DC. line 118 and the conductor119.

In operation, currents flowing through the primary windings 47, 80, and81 of the power transformer 19 induce voltages in the secondary windings82, 83, and 84, and in the ternary windings 85, 86, and 87. The outputvoltages trom the windings 82, 83, and 84 are taken from the points a,b, and c, The voltages developed in the ternary windings 85-87 areapplied through the bridge rectifier G through the resistor 114 anddiodes 111 and 112 to the base 10112 of the transistor 101. The voltageapplied to the base 101b is a rectified average of the three phaseoutput from the ternary windings 85-87. The Zener diodes 111-113collectively provide a DC. reference voltage with which the rectifiedaverage voltage is compared for establishing a diflerence voltage. Thisdifterence voltage applied to the base 101]) is amplified by thetransistors 101, 102, and 103. The difference be tween the averagerectified voltage and the reference level established by the Zenerdiodes 111-113 controls the amount of current flowing through thewindings 95-97. Current flowing through the control windings 95-97changes the inductance of the saturable reactors 89-91, respectively.

The secondary windings 98-100 as aifected by the control windings 95-97and the capacitors 92-94, respectively, cooperate to provide a constantpower factor to the output terminals A, B, and C. The voltage regulatorcircuit 20 thereby provides a constant output voltage, notwithstandingvarying load conditions.

6 The components utilized in the circuits shown and described abovepreferably may be of the types or have values as follows.

Shift register 23 (FIG. 2):

Core 27 Wrap 1 mil Deltamax tape on A22 bobbin. Shift winding 28 20turns. Input winding 29 40 turns. Output winding 30 40 turns. 10 Resetwinding 31 10 turns.

Capacitor 35 .038 mfd. i Inductor 36 -1 9.7 mh.

Resistor 37 300 ohms. 1r Silicon diode 38 HD6751.

" Controlled rectifier circuit -16 (FIG. 2

Controlled rectifiers 42, 48 C35A. Transistors 43, 49 2N65 6. Silicondiodes 44, 50 HD6751. Capacitor 51 8 mfd.

Pulse generator 11 (FIG. 3):

Unijunction transistor 60 2N49l. Transistor 61 2N656. Capacitor 62 50mfd.

Capacitor 63 .04 mfd. Capacitor 64 .25 mfd. Capacitor 65 .01 mfd.Resistor 66 120 ohms. Resistor 67 10K ohms.

Resistor (sensistor) 68 120 ohms. Resistor 69 150 ohms. Resistor 70 10ohms. Variable resistor 71 0 to 5K ohms.

Voltage regulator 20 (FIG. 4):

Saturable reactors 89, 90, 91

Transistor 101 2N656. Transistor 102 HA7505. Transistor 103 2N389.Silicon diodes 104-109 HD6751. Silicon diode WE302A. Zener diode 111 11volts. Zener diode 112 11 volts. Zener diode 113 8 volts. Resistor 114100 ohms. Resistor 115 1K ohms.

It is contemplated that the entire inverter 10, with the exception ofthe input and output terminals, may be mounted on printed circuits andsealed within a suitable container and potted with parafiin or othersuitable potting material. Such a construction should render the circuitrelatively free from environmental conditions and substantiallyshockproof.

There has been provided by this invention a new and improved staticinverter which is capable of converting a direct current voltage into apolyphase alternating voltage. This inverter is light in weight, highlyefficient, and has reliability unsurpassed by any comparable device.

It is to be understood that this invention is not to be limited to thespecific constructions and arrangements shown and described except onlyinsofar as the appended claims may be so limited, as it will be apparentto those skilled in the art that changes may be made without departingfrom the principles of the invention.

I claim:

1. In an electrical circuit for converting direct current voltage intoalternating current voltage, the combination of controlled currentconducting means, means for applying a direct current voltage to saidconducting means to energize the same, gate circuit means coupled tosaid conducting means for operating the same, means in said gate circuitmeans for conditioning said gate circuit means for operation insequence, time delay means in said gate circuit means for delaying theconditioning thereof, and timing generator means coupled to said gatecircuit means for triggering the conditioned gate circuit means intooperation.

2. In an electrical circuit for converting direct current voltage intoalternating current voltage, the combination of a plurality ofcontrolled current conducting means; means for applying a direct currentvoltage to said conducting means to energize the same; a plurality ofmagnetic shift registers coupled to said conducting means for operatingthe same, each of said shift registers comprising a magnetic core, aninput winding for magnetizing said core, an output Winding operative inresponse toa change in magnetization of said core to provide a controlsignal, and a shift winding coupled to said core for changing thedirection of magnetization thereof; means for applying said controlsignal both to one of said conducting means and to an input winding of asucceeding shift register; and timing generator means coupled to saidshift windings for energizing them.

3. In a static inverter, the combination of a plurality of controlledrectifier circuits; means for applying a direct current voltage to saidcontrolled rectifier circuits to energize the same; a plurality ofmagnetic shift registers coupled to said rectifier circuits foroperating same; timing generator means coupled to said shift registersto operate said registers inaccordance with a predetermined sequence,said shift registers each comprising a magnetic core, an input windingfor magnetizing said core, an output winding operative in response to achange in magnetization of said core to provide a control signal, ashift winding coupled to said timing means for changing themagnetization of said core, and areset winding also cou pled to saidcore; means for applying said control signal both to one of saidrectifier circuits and to an input winding of another shift register;and means for energizing said reset windings for establishing theinitial operating conditions of said shift registers.

4. In an electrical circuit for converting direct current voltage intoalternating current voltage, the combination of a plurality ofcontrolled current conducting means; means for applying a direct currentvoltage to said conducting means to energize same; a plurality ofmagnetic shift registers coupled to said conducting means for operatingsame; timing. generator means coupled to said I shift registers tooperate them, each of said shift registers comprising a magnetic core,an input winding for magnetizing said core, an output winding operativein response to a change in the magnetization of said core to provide acontrol signal, and a shift winding coupled to said timing means forchanging the magnetization of said core; means for applying said controlsignal to one of said conducting means; and time delay or temporarystorage means inter-coupling an output winding of one shift registerwith an input winding of another shift register.

5. In a polyphase static inverter for converting direct current voltagereceivedover an input circuit into three phase alternating currentvoltage, the combination of three pair of controlled rectifier circuits;means for ap- 8 plying a direct current voltage to said rectifiercircuits to energize the same; six magnetic shift registers coupled tosaid rectifiers in a predetermined manner; a timing pulse generatorcircuit coupled to said shift registers to effect operation thereof,each of said shift registers comprising a magnetic core, an inputwinding for magnetizing said core, an output winding for detecting achange in the direction of magnetization of said core and coupled bothto one of said rectifier circuits and to an input Winding of asucceeding shift register, a reset winding for coupling to said inputcircuit for establishing the initial direction of magnetization of eachof said cores, and a shift winding coupled to said timing pulsegenerator circuit for shift-ing the direction of magnetization of saidcore for thereby controlling the conduction of one of said rectifiercircuits.

6. In a. static inverter including translation means for providing anA.C. output signal responsive to receipt of DC. pulse signals, thecombination of a plurality of selective conduction means coupled to saidtranslation means, a like plurality of gate circuits, each gate circuitbeing conditioned upon receipt of an output signal from a preceding gatecircuit to operate at a later time determined by receipt of a controlsignal and produce an output signal, a first output circuit intercoupledbetween each of said gate circuits and one of said selective conduotionmeans to pass an output signal between one gate circuit and theassociated conduction means and thus provide a DC. pulse signal to thetranslation means, a second output circuit including time delay meansintercoupled between each gate circuit and the next successive gatecircuit operative to delay by a given time interval the passage of theoutput signal from one gate circuit to the next successive gate circuit,and timing gen erator means coupled to each of said gate circuitso-perative to simultaneously apply a control signal to each gatecircuit, the time duration of said control signal being less than saidgiven time interval, thereby providing an output signal from the gatecircuit previously conditioned for operation and conditioning the nextsuccessive gate circuit for operation upon receipt of the next controlsignal.

References Cited in the file of this patent UNITED STATES PATENTS1,904,455 Hazeltine Apr. 18, 1933 2,548,737 Morris Apr. 10, 19512,567,410 Trousdale Sept. 11, 1951 2,734,164 Knowlton Feb. 7, 19562,824,274 Holt Feb. 18, 1958 2,885,627 Holt May 5, 1959 2,912,634Peoples Nov. 10, 1959 2,916,687 Cronin Dec. 8, 1959 OTHER REFERENCESTrans-istorized Three-Phase Power Supplies, by W. Brannian, published inElectronic Industries (January 1959), pp. 2-5.

5. IN A POLYPHASE STATIC INVERTER FOR CONVERTING DIRECT CURRENT VOLTAGERECEIVED OVER AN INPUT CIRCUIT INTO THREE PHALE ALTERNATING CURRENTVOLTAGE, THE COMBINATION OF THREE PAIR OF CONTROLLED RECTIFIER CIRCUITS;MEANS FOR APPLYING A DIRECT CURRENT VOLTAGE TO SAID RECTIFIER CIRCUITSTO ENERGIZE THE SAME; SIX MAGNETIC SHIFT REGISTERS COUPLED TO SAIDRECTIFIERS IN A PREDETERMINED MANNER; A TIMING PULSE GENERATOR CIRCUITCOUPLED TO SAID SHIFT REGISTERS TO EFFECT OPERATION THEREOF, EACH OFSAID SHIFT REGISTERS COMPRISING A MAGNETIC CORE, AN INPUT WINDING FORMAGNETIZING SAID CORE, AN OUTPUT WINDING FOR DETECTING A CHANGE IN THEDIRECTION OF MAGNETIZATION OF SAID CORE AND COUPLED BOTH TO ONE OF SAIDRECTIFIER CIRCUITS TO AN INPUT WINDING OF A SUCCEEDING SHIFT REGISTER, ARESET WINDING FOR COUPLING TO SAID INPUT CIRCUIT FOR ESTABLISHING THEINITIAL DIRECTION OF MAGNETIZATION OF EACH OF SAID CORES, AND A SHIFTWINDING COUPLED TO SAID TIMING PULSE GENERATOR CIRCUIT FOR SHIFTING THEDIRECTION MAGNETIZATION OF SAID CORE THEREBY CONTROLLING THE CONDUCTIONOF ONE OF SAID RECTIFIER CIRCUITS.